The present invention relates to a double-gate flash memory device formed on a bulk silicon substrate. More particularly, the invention relates to the structure of a flash memory device which has higher integration density and better program/erase characteristic in comparison to prior art flash memory devices.
A flash memory device has many practical applications, apart from the use in memory itself, it could also be used in various types of electronic apparatus.
A flash memory device is found to be especially suitable for the recently developed embedded logic technology and shows a good process compatibility with the logic technology during the fabrication process.
A highly functional and integrated flash memory device, apart from the use in memory itself, has the potential to bring significant added values in conjunction with logic technology. This fact has attracted a large amount of research activities in this area around the world.
As the size of a Complementary Metal-Oxide Semiconductor (CMOS) silicon semiconductor device is being reduced to 100 nm or below, the power consumption is reduced and the integration density is enhanced to allow the implementation of a very fast VLSI device possible. Consequently, it has resulted a reduction in the size of various electronic systems and brought about a significant improvement in the system performance through the decrease in the power consumption.
This was mainly possible due to the good scaling down characteristics of CMOS devices. The gate size of these devices is being continuously scale-downed up to a channel size of sub-50 nm. In addition to the scaling down of these CMOS devices, the characteristics of flash memory devices that utilize the advanced CMOS fabrication process should be improved in order to bring about significant added values.
Hereinafter, the prior art flash memory devices will be described in detail with reference to the accompanying drawings.
FIG. 1a and FIG. 1b show an example of scaling down of a conventional flash memory device.
Looking into FIG. 1b in comparison to FIG. 1a, it is noticed that the gate height and the junction depth as well as the channel length are reduced, however, the thickness between a tunneling oxide film (66) and a storage electrode (68) and that of the inter-gates oxide film (70) between a floating electrode and a control electrode (72) are not reduced.
A conventional metal-oxide semiconductor (MOS) device can easily restrain a short-channel effect by using a thin gate oxide film according to the scaling down, however, a flash memory device cannot be scaled down easily due to non-scalable gate insulators.
A flash memory device has a similar configuration to a conventional CMOS device except having a storage electrode (68) for storing electric charges between a control electrode (20) and a channel of the device.
A tunneling oxide film (66) is constituted under the storage electrode (68), and the thickness of a tunneling oxide film (66) cannot be reduced with the scaling down.
If the thickness of the tunneling oxide film (66) is reduced, the charges stored in the storage electrode (68) leaks back to the channel, and thus the retention characteristic of a memory becomes to deteriorate.
Hence, it is necessary to employ various types of methods to resolve this problem. As shown in FIG. 1, the thickness of the tunneling oxide film (66) of a flash memory device in the prior art could not be reduced. This is the main reason why the channel length of a flash memory device could not be reduced in spite of the advanced CMOS technology environment.
More specifically, in order to reduce the channel length of a flash memory device, the thickness of the tunneling oxide film (66) which corresponds to a gate oxide film in a CMOS device should be reduced.
However, if the thickness of the tunneling oxide film (66) is reduced, then the important retention characteristic for memory could not be guaranteed.
Eventually, the values of the present flash memory devices are bound to fall sooner or later.
Fortunately, researches on Silicon-Oxide-Nitride-Oxide-Semiconductor (SONOS) type flash memory device, which has a somewhat modified configuration compared with that of a conventional flash memory device, are currently being carried on.
The configuration of SONOS type device is the same as that of FIG. 1a and FIG. 1b with the substance of the storage electrode (68) being substituted with a silicon nitride film (Si3N4).
In an SONOS type flash memory device, however, the thickness of Oxide-Nitride-Oxide (ONO) film, which corresponds to a gate oxide film in a CMOS device, is still thicker than that of the gate oxide film (for example, 2 nm/4 nm/4 nm), and thus the scaling down characteristic is worse than that of CMOS device having the same gate length.
Additionally, there exist traps, in which charges can be stored, in the nitride film corresponding to N in an ONO-structure, and thus charges are trapped therein during a writing program.
Since the trap density is non-uniform, it requires gate length and width over a certain minimum value, and thus it has a limitation in improving integration density.
From the researches of conventional CMOS devices, a double-gate device formed on a SOI silicon substrate is appearing in the recent publications. The characteristic of this device shows that it could have the shortest channel length amongst the known devices to date.
FIG. 2a and FIG. 2b show that an example of a double-gate device formed on a SOI silicon substrate (2a) either in a transparent or non-transparent diagram.
The double-gate device constitutes a gate electrode (76) on either side of the channel (or top and bottom) in order to achieve a significant improvement on the short channel effect.
Since all of the conventional double-gate MOS devices are formed on a SOI substrate, the SOI wafer has the disadvantage of being more expensive than a bulk wafer. Also, the conventional double-gate MOS devices have the problem of a floating body problem.
Moreover, Buried Oxide (BOX) formed on a SOI silicon substrate (2a) blocks the heat conduction from the device to the SOI silicon substrate (2a), resulting in deterioration of the device characteristic.